Of course you hear more and more termino 3d packagingand over time it will become more important. The first 3D packages are already on sale, as is the case with AMD and its 3D V-Cache. In this article, you will learn a little more about these types of packaging and their relevance.
What is a 3D package?
Packaged microcircuits are located on a printed circuit board, which are connected to each other by thin wires. in all kinds 3D packagingThe microcircuits in the package communicate with an external signal, as if they were mounted in separate packages on a common printed circuit board. Intel 3D processors, HBM memory, and other chips use small micro-copper windings as a connection inside the package with the chip flip process.
Technique called. called hybrid binding Stacks and interconnects chips using small copper-to-copper interconnects, providing higher density and performance than existing chip stacking interconnects. Hybrid copper bonding, a relatively new process performed in a semiconductor manufacturing plant, is a state-of-the-art chip stacking technology that promises to offer some competitive advantages to chip customers. The first wave of chips launched on the market using this technology, called hybrid bonding, paves the way for a new competitive era of 3D chip products and advanced packaging.
AMD became the first supplier Which introduced copper junction hybrid ICs, a state-of-the-art die-combining technology that enables the creation of next-generation 3D-like devices and packages. This technology, called hybrid bonding, offers several new possibilities for high-end designs, paving the way for next-generation 3D designs, 3D RAM chips, and even more advanced packaging. Hybrid bonding is a key technology that is valuable in wafer-to-wafer bonding and equally attractive in wafer-to-chip bonding.
In this case, the interconnect technology decides how the arrays are placed and joined together. alone in 2D. in conventional electronic circuits, each array is packed separately. Array stacks are much closer on 3D chips than on PCBs.
The chip must be designed with the matrix stack in mind and takes special equipment To align and join them. First, each array on the stack must be designed with stacking in mind, and this requires significant design effort. In fact, multi-chip stacks can include combinations that are not possible with 2D chips.
Instead of chipset alignment (thus 2D) horizontally connected arrays, each contained in its own small bag or box to protect it from corrosive attack, more sophisticated technologies now stack the chips vertically (thus in 3D) in an equally small box, the contents of which make up the entire package. Today, the industry uses the most advanced packaging techniques to fit multiple high quality and/or mature chips into a single package, also known as heterogeneous integration.
Rollers meet new needs
As chips become more and more complex, advanced packaging technologies are becoming a potential area for technological breakthroughs. Innovative multi-chip packaging and interconnect technologies are expected to be critical to advanced processors in the coming years, which is why every major chip designer and manufacturer has developed their own proprietary chip layouts and interconnect techniques. Other contract semiconductor manufacturers (TSMC, GlobalFoundries), Integrated Circuit Manufacturer (Intel, Samsung) and even chip developers without a factory (AMD), who can access the latest manufacturing equipment and manufacturing processes, package and connect 2.5D and 3D chips to offer their customers or their future products. development of own methods.
These companies cannot access construction equipment Fabrication technologies are required to produce chips smaller than 10 nm, so advanced packaging and connection techniques are also important to SMIC. Many chip manufacturers have this type of 3D packaging technology, including Intel’s competitor TSMC.
One goal, different paths
On the basis of technology, the semiconductor 3D packaging market has been divided into 3D silicon through holes, 3D packaging on the package, 3D fan base, 3D wire connection and others. one of forms The segmentation of the packaging market is based on interconnect types, including wire connection, flip-chip, wafer-level packaging (WLP), and end-to-end through-silicon (TSV).
in examples 3D packaging These include POP packaging, in which individual arrays are packaged, packages are stacked on top of each other, and interconnects are made using a wire-connection or flip-chip process; and three-dimensional wafer-level packaging (3D WLP), which uses redistribution layers (RDL) and an overlay process to create interconnects. Despite the push for higher packing densities, many of these devices are still based on older technologies such as wire bonding and flip chips.
Small size and low power consumption are the main factors driving the demand for chips with various advanced semiconductor packaging technologies, one of which is 3D packaging design. 3D packaging This allows chip designers to use expensive tiles made with technology when they matter, like the brains of processor chips, and then use older technology when speed isn’t as important, reducing costs. . The new race in chip manufacturing is to pack chips – small square pieces of what is usually a big chip – into a package stacked on top of a silicon base layer, rather than trying to make one big chip. Mix and match different techniques.
Intel has provided some high-level details about the new technology called fovros, a 3D packaging technology that will debut next year that will allow complex and diverse logic chips to be stacked directly on top of each other next year. To that end, Applied Materials — the company that builds all the machines used by Intel, TSMC, Samsung, GloFo, and every other Samsung semiconductor manufacturer — and the A*STAR Microelectronics Institute (IME) announced the launch of -the-art, a state-of-the-art 3D chip packaging lab. in Singapore. Taiwan’s leading semiconductor foundry plans to open a wafer plant in the US, but it is the Japanese alliance that is in talks to develop advanced packaging technology.
To support ourselves, innovation in chip packaging and Interworking Technologies According to DigiTimes, Guo Ping, a retired president of Huawei, said at a recent press conference that chip stacking in general, and 3D stacking in particular, could allow Huawei to pack more transistors into its SoCs. and can achieve the performance needed to compete. This type of 3D chip packaging is rapidly improving and becoming more relevant as the required features in the smaller elements to be included in the package, wafer fragments called crystals, are reduced to 3 nanometers and smaller nodes. In general, 3D integration is a broad term that includes technologies such as wafer-level 3D packaging; Integration based on 2.5D and 3D interposers; 3D composite (3D-sic) and 3D monolithic ICs; Heterogeneous 3D integration and integration of 3D systems.
3D semiconductor packaging technology is also expected to benefit from affordability new material packaging such as printed circuit boards. The demand for miniaturization of memory chips, the need for high-bandwidth electronics, and cost control requirements are expected to further drive demand for 3D semiconductor packages. Demand for 3D packaged ICs is expected to increase due to strong investment in R&D by some major players such as Amcor Technology, ASE Group and Siliconware Precision Industries Co., Ltd., leading to an improvement in the high-end segment . . packaging technology. Further development of 3D POP technology is expected, in which application processors use advanced innovations based on smaller chips that inspect packets faster according to common configurations. ,
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Probably more penetration Wireless and IoT devices Open up new possibilities and let this technology increase its market share in high quality packaging. Technological advantages of 3D packaging The advantages of 3D packaging increase its demand in high performance applications such as chips used in supercomputers, DRAMS, NAND, microelectronic circuits, etc.